Every chip starts life as a sand crystal refined to 99.9999999% purity and a catalog of specialty chemicals so exotic that most have fewer than two global suppliers. This is the layer nobody talks about - and the one whose disruption can idle every fab on earth within weeks.
Controls ~30% of global 300mm wafer supply alongside Sumco. Together they ship more than half the world's silicon blanks - a duopoly so tight that a single Niigata earthquake reshapes global fab schedules.
After its $6.5B acquisition of CMC Materials in 2022, now the dominant global supplier of CMP slurries, advanced filtration, and specialty chemicals to every major foundry. One product recall cascades everywhere.
One of fewer than five companies globally that can manufacture EUV-grade photomasks. Lead times for a full advanced mask set: 8–16 weeks, with zero substitutes at leading-edge nodes.
The machines that build chips are more complex than the chips themselves - ASML's EUV lithography tool contains 100,000+ parts, costs $380M, and requires 40 Boeing 747 flights to deliver. Every advanced chip on earth passes through one factory in Veldhoven, Netherlands.
The only company on earth that makes EUV lithography machines - essential for every chip below 7nm. Revenue: €27.6B. Backlog: €36B+. Export restrictions have blocked China from receiving EUV tools since 2019.
With Lam Research, forms a near-duopoly in deposition and etch tools - steps performed 1,000+ times per wafer. Both subject to aggressive US export controls targeting Chinese leading-edge fabs.
Dominates process control and wafer inspection - without KLA, yield collapses. At 2nm nodes, a single-atom defect can kill a chip. KLA holds 50%+ share in several critical inspection categories.
Modern chips contain 100 billion transistors - no human can design one without software, and that software is owned entirely by two US companies. US export controls on EDA tools are the sharpest technology sanction available to Washington: they can stop an adversary from designing advanced chips without touching a single physical good.
World's largest EDA company. Revenue: $6.1B. Every advanced chip - Apple A18, NVIDIA H100, every Qualcomm Snapdragon - passes through Synopsys tools before tape-out.
Licenses the processor architecture inside 95%+ of smartphones. NVIDIA's $40B acquisition was blocked by global regulators. ARM went public in 2023 at a $54B valuation; SoftBank retains majority ownership.
The second EDA giant. Revenue: $4.3B. Dominant in analog/RF chip design and physical verification. Cadence and Synopsys together are a duopoly any chip design ecosystem must navigate or be blocked by.
The most famous layer - the NVIDIAs, the Apples, the Qualcomms - captures the highest margins in the entire supply chain while owning not a single fab or etching tool. Fabless chip design is a $400B/year business built on one insight: it's more profitable to think than to manufacture.
H100 GPU: $30,000–40,000 each, 75%+ gross margin, $3T+ market cap in 2024. Its CUDA software stack - 15 years in the making - is as much a moat as the silicon itself.
Designs the world's most performant mobile chips with ~3,000 engineers, then purchases 20–25% of TSMC's leading-edge wafer capacity. The most influential chip customer on earth.
Its switching ASICs route data across every hyperscaler's data center. Custom AI accelerators (XPUs) built for Google and Meta represent one of the fastest-growing segments in semiconductors.
This is where physics meets policy - rooms cleaner than outer space, robots operating at atomic tolerances, processes that take three to six months per lot. TSMC makes 90%+ of the world's most advanced chips in one small country, and the entire trajectory of AI, consumer electronics, and modern warfare rests on that island remaining peaceful.
Revenue: $90B+ (2024). Makes 90%+ of chips below 5nm. The US, EU, and Japan are spending hundreds of billions to diversify away from a single island - and know they cannot fully succeed within this decade.
The world's leading supplier of HBM - the stacked DRAM that sits next to NVIDIA's H100 and H200 GPUs. Without HBM, AI training clusters cannot be built. SK Hynix supplies ~50% of total HBM output.
China's most advanced domestically owned foundry. Capable of ~7nm using legacy multi-patterning. Its technical ceiling is set not by capital but by the equipment it's permitted to import.
Packaging was once an afterthought; it is now the frontier where AI chip performance is won or lost - stacking dies with micron-precision bonds, collapsing the distance electrons must travel. The bottleneck that choked AI infrastructure buildout in 2023 wasn't wafer fab capacity. It was TSMC's CoWoS packaging line.
The advanced packaging technology that bonds HBM memory and GPU die in one package, enabling NVIDIA's H100 and H200. TSMC has tripled CoWoS capacity; demand still consistently outpaces supply.
Processes ~40% of global chip packages. Revenue: $18B+. The world's largest OSAT. As advanced packaging replaces node scaling as the primary performance lever, ASE's strategic importance compounds.
World's largest ATE maker. AI chips are so complex that test time per device has grown 3–5× versus prior generations - directly expanding Advantest's revenue and backlog.
The $600B semiconductor industry is ultimately steered by fewer than a dozen companies - Apple, four hyperscalers, and a handful of automakers placing orders 18 months before a product ships. These customers don't just buy chips; they finance leading-edge node economics, and the companies that control their procurement cycles control the industry's roadmap.
AWS, Microsoft, Google, and Meta collectively plan $300B+ in capex in 2025. For NVIDIA, the binding constraint on revenue is not price or competition - it's wafer and CoWoS packaging allocation.
Places TSMC wafer orders 18–24 months ahead. Accounts for 20–25% of TSMC's total revenue. Its annual A-series and M-series cadence effectively sets TSMC's process development calendar.
A modern EV contains $1,000–2,000 in semiconductor content vs ~$400 for an ICE vehicle. Tesla designs its own FSD and Dojo AI chips in-house - the most technology-integrated automaker by a significant margin.
Four stand out: EUV lithography (ASML alone), leading-edge foundry capacity (TSMC and Samsung), EUV-grade photomasks (fewer than five suppliers, 8–16 week lead times), and advanced packaging such as CoWoS. Below them sit silicon wafers, where Shin-Etsu and Sumco ship over half of global supply.
TSMC manufactures the large majority of the world’s leading-edge logic chips, including the AI accelerators designed by fabless companies like NVIDIA, AMD and Apple. Concentration of that capacity on one island makes Taiwan a single point of failure for advanced computing.
A fabless company designs chips but owns no factory, contracting manufacturing to a foundry such as TSMC. NVIDIA, AMD, Qualcomm, Broadcom and Apple are fabless. The model separates chip design economics from the enormous fixed cost of building fabs.